default search action
ISLPED 2022: Boston, MA, USA
- Hai Helen Li, Charles Augustine, Ayse Kivilcim Coskun, Swaroop Ghosh:
ISLPED '22: ACM/IEEE International Symposium on Low Power Electronics and Design, Boston, MA, USA, August 1 - 3, 2022. ACM 2022, ISBN 978-1-4503-9354-6
Session 1: Energy-efficient and Robust Neural Networks
- Abhiroop Bhattacharjee
, Youngeun Kim, Abhishek Moitra, Priyadarshini Panda:
Examining the Robustness of Spiking Neural Networks on Non-ideal Memristive Crossbars. 1:1-1:6 - Deepika Sharma
Identifying Efficient Dataflows for Spiking Neural Networks. 2:1-2:6 - Jung Hwan Heo, Arash Fayyazi, Amirhossein Esmaili, Massoud Pedram:
Sparse Periodic Systolic Dataflow for Lowering Latency and Power Dissipation of Convolutional Neural Network Accelerators. 3:1-3:6
Session 2: Novel Computing Models (Chair: Priyadarshini Panda, Yale)
- Cheng Chu, Nai-Hui Chia, Lei Jiang, Fan Chen:
QMLP: An Error-Tolerant Nonlinear Quantum MLP Architecture using Parameterized Two-Qubit Gates. 4:1-4:6 - Chao Lu, Shamik Kundu, Abraham Peedikayil Kuruvila, Supriya Margabandhu Ravichandran, Kanad Basu:
Design and Logic Synthesis of a Scalable, Efficient Quantum Number Theoretic Transform. 5:1-5:6 - Joonhyung Kim, Kyeongho Lee, Jongsun Park:
A Charge Domain P-8T SRAM Compute-In-Memory with Low-Cost DAC/ADC Operation for 4-bit Input Processing. 6:1-6:6
Session 3: Efficient and Intelligent Memories (Chair: Kshitij Bhardwaj, LLNL)
- Ranyang Zhou, Arman Roohi, Durga Misra, Shaahin Angizi:
FlexiDRAM: A Flexible in-DRAM Framework to Enable Parallel General-Purpose Computation. 7:1-7:6 - Ya-Hui Yang, Shuo-Han Chen, Yuan-Hao Chang:
Evolving Skyrmion Racetrack Memory as Energy-Efficient Last-Level Cache Devices. 8:1-8:6 - Swati Upadhyay, Arijit Nath, Hemangee K. Kapoor:
Exploiting successive identical words and differences with dynamic bases for effective compression in Non-Volatile Memories. 9:1-9:6
Session 4: Circuit Design and Methodology for IoT Applications (Chair: Hun-Seok Kim, UMich)
- Tianrui Ma
HOGEye: Neural Approximation of HOG Feature Extraction in RRAM-Based 3D-Stacked Image Sensors. 10:1-10:6 - Ruicong Chen, H. T. Kung, Anantha P. Chandrakasan, Hae-Seung Lee:
A Bit-level Sparsity-aware SAR ADC with Direct Hybrid Encoding for Signed Expressions for AIoT Applications. 11:1-11:6 - Shida Zhang
Analysis of the Effect of Hot Carrier Injection in An Integrated Inductive Voltage Regulator. 12:1-12:6
Session 5: Advances in Hardware Security (Chair: Apoorva Amarnath, IBM)
- Zahra Azad, Guowei Yang
RACE: RISC-V SoC for En/decryption Acceleration on the Edge for Homomorphic Computation. 13:1-13:6 - Jingyao Zhang
Sealer: In-SRAM AES for High-Performance and Low-Overhead Memory Encryption. 14:1-14:6
Session 6: Novel Physical Design Methodologies (Chair: Marisa Lopez Vallejo, UPM)
- Anthony Agnesina, Moritz Brunion, Alberto García Ortiz, Francky Catthoor, Dragomir Milojevic
Hier-3D: A Hierarchical Physical Design Methodology for Face-to-Face-Bonded 3D ICs. 15:1-15:6 - Jaehoon Jeong
A Study on Optimizing Pin Accessibility of Standard Cells in the Post-3 nm Node. 16:1-16:6 - Sehyeon Chung, Jooyeon Jeong, Taewhan Kim:
Improving Performance and Power by Co-Optimizing Middle-of-Line Routing, Pin Pattern Generation, and Contact over Active Gates in Standard Cell Layout Synthesis. 17:1-17:6
Session 7: Enablers for Energy-efficient Platforms (Chair: Xue Lin, Northeastern)
- Berken Utku Demirel, Luke Chen, Mohammad Abdullah Al Faruque:
Neural Contextual Bandits Based Dynamic Sensor Selection for Low-Power Body-Area Networks. 18:1-18:6 - Lingjun Zhu, Nesara Eranna Bethur, Yi-Chen Lu, Youngsang Cho, Yunhyeok Im, Sung Kyu Lim:
3D IC Tier Partitioning of Memory Macros: PPA vs. Thermal Tradeoffs. 19:1-19:6 - Yigit Tuncel, Anish Krishnakumar, Aishwarya Lekshmi Chithra, Younghyun Kim, Ümit Y. Ogras
A Domain-Specific System-On-Chip Design for Energy Efficient Wearable Edge AI Applications. 20:1-20:6
Session 8: System Design for Energy-efficiency and Resiliency (Chair: Aatmesh Shrivastava, Northeastern)
- Yen-Ting Chen
SACS: A Self-Adaptive Checkpointing Strategy for Microkernel-Based Intermittent Systems. 21:1-21:6 - Yi-Shen Chen, Yuan-Hao Chang, Tei-Wei Kuo:
Drift-tolerant Coding to Enhance the Energy Efficiency of Multi-Level-Cell Phase-Change Memory. 22:1-22:6 - Yufan Yue
A Unified Forward Error Correction Accelerator for Multi-Mode Turbo, LDPC, and Polar Decoding. 23:1-23:6
Poster Session
- Cheng Chu, Dawen Xu, Ying Wang, Fan Chen:
Canopy: A CNFET-based Process Variation Aware Systolic DNN Accelerator. 24:1-24:6 - Abinand Nallathambi, Sanchari Sen, Anand Raghunathan, Nitin Chandrachoodan:
Layerwise Disaggregated Evaluation of Spiking Neural Networks. 25:1-25:6 - Suwan Kim, Sehyeon Chung, Taewhan Kim, Heechun Park:
Tightly Linking 3D Via Allocation Towards Routing Optimization for Monolithic 3D ICs. 26:1-26:6 - Alberto Marchisio
Enabling Capsule Networks at the Edge through Approximate Softmax and Squash Operations. 27:1-27:6 - Matteo Risso, Alessio Burrello
Multi-Complexity-Loss DNAS for Energy-Efficient and Memory-Constrained Deep Neural Networks. 28:1-28:6 - Alessandro Torrisi
Visible Light Synchronization for Time-Slotted Energy-Aware Transiently-Powered Communication. 29:1-29:6 - Abhinav Goel, Caleb Tung, Nick Eliopoulos, Xiao Hu, George K. Thiruvathukal, James C. Davis, Yung-Hsiang Lu:
Directed Acyclic Graph-based Neural Networks for Tunable Low-Power Computer Vision. 30:1-30:6 - Reena Elangovan, Ashish Ranjan, Niharika Thakuria, Sumeet Kumar Gupta, Anand Raghunathan:
Energy Efficient Cache Design with Piezoelectric FETs. 31:1-31:6 - Prattay Chowdhury, Chaitali Sathe, Benjamin Carrión Schäfer:
Predictive Model Attack for Embedded FPGA Logic Locking. 32:1-32:6
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-11-15 19:20 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: