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31st FCCM 2023: Marina Del Rey, CA, USA
- 31st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2023, Marina Del Rey, CA, USA, May 8-11, 2023. IEEE 2023, ISBN 979-8-3503-1205-8
- Rishov Sarkar
, Cong Hao:
LightningSim: Fast and Accurate Trace-Based Simulation for High-Level Synthesis. 1-11 - Moazin Khatti, Xingyu Tian, Yuze Chi, Licheng Guo, Jason Cong, Zhenman Fang:
PASTA: Programming and Automation Support for Scalable Task-Parallel HLS Programs on Modern Multi-Die FPGAs. 12-22 - Zhuanhao Wu, Maya B. Gokhale, Scott Lloyd, Hiren D. Patel:
SCCL: An open-source SystemC to RTL translator. 23-33 - Xiaochen Hao, Mingzhe Zhang, Ce Sun, Zhuofu Tao, Hongbo Rong, Yu Zhang, Lei He, Eric Petit, Wenguang Chen, Yun Liang:
Lasa: Abstraction and Specialization for Productive and Performant Linear Algebra on FPGAs. 34-40 - Srivatsan Srinivasan, Andrew Boutros, Fatemehsadat Mahmoudi, Vaughn Betz:
Placement Optimization for NoC-Enhanced FPGAs. 41-51 - Yuzong Chen, Mohamed S. Abdelfattah:
BRAMAC: Compute-in-BRAM Architectures for Multiply-Accumulate on FPGAs. 52-62 - Andrew David Gunter
A Machine Learning Approach for Predicting the Difficulty of FPGA Routing Problems. 63-74 - Chenjiu Wang, Ke He, Ruiqi Fan, Xiaonan Wang, Wei Wang, Qinfen Hao:
CXL over Ethernet: A Novel FPGA-based Memory Disaggregation Design in Data Centers. 75-82 - Yuhao Ding, Jiajun Wu, Yizhao Gao, Maolin Wang, Hayden Kwok-Hay So
Model-Platform Optimized Deep Neural Network Accelerator Generation through Mixed-Integer Geometric Programming. 83-93 - Jiajun Wu, Jiajun Zhou, Yizhao Gao, Yuhao Ding, Ngai Wong, Hayden Kwok-Hay So:
MSD: Mixing Signed Digit Representations for Hardware-efficient DNN Acceleration on FPGA with Heterogeneous Resources. 94-104 - Alireza Khataei, Gaurav Singh, Kia Bazargan:
Optimizing Hybrid Binary-Unary Hardware Accelerators Using Self-Similarity Measures. 105-113 - Pengzhou He, Tianyou Bao
Efficient Implementation of Ring-Binary-LWE-based Lightweight PQC Accelerator on the FPGA Platform. 114-120 - Benjamin Biggs, Christos-Savvas Bouganis, George A. Constantinides:
ATHEENA: A Toolflow for Hardware Early-Exit Network Automation. 121-132 - Abhishek Kumar Jain, Chirag Ravishankar, Hossein Omidian, Sharan Kumar, Maithilee Kulkarni, Aashish Tripathi, Dinesh Gaitonde:
Modular and Lean Architecture with Elasticity for Sparse Matrix Vector Multiplication on FPGAs. 133-143 - Petros Toupas
HARFLOW3D: A Latency-Oriented 3D-CNN Accelerator Toolflow for HAR on FPGA Devices. 144-154 - Lukas Huegle, Martin Gotthard, Vincent Meyers, Jonas Krautter, Dennis R. E. Gnad, Mehdi B. Tahoori:
Power2Picture: Using Generative CNNs for Input Recovery of Neural Network Accelerators through Power Side-Channels on FPGAs. 155-161 - Xin Wu, Tobias Kenter, Robert Schade
Computing and Compressing Electron Repulsion Integrals on FPGAs. 162-173 - Yuying Zhang, Sathi Sarveswara Reddy, Zili Kou, Sharad Sinha, Wei Zhang:
Tensor-Product-Based Accelerator for Area-efficient and Scalable Number Theoretic Transform. 174-183 - Alec Lu, Zhenman Fang:
SQL2FPGA: Automatic Acceleration of SQL Query Processing on Modern CPU-FPGA Platforms. 184-194 - Hanqiu Chen, Cong Hao:
DGNN-Booster: A Generic FPGA Accelerator Framework For Dynamic Graph Neural Network Inference. 195-201 - Chris Keilbart, Yuhui Gao, Martin Chua, Eric Matthews, Steven J. E. Wilton, Lesley Shannon:
Designing a configurable IEEE-compliant FPU that supports variable precision for soft processors. 202 - Geng Yang, Jie Lei, Zhenman Fang, Yunsong Li, Jiaqing Zhang
HyBNN: Quantifying and Optimizing Hardware Efficiency of Binary Neural Networks. 203 - Fumiya Kono, Naohito Nakasato, Maho Nakata:
Accelerating 128-bit Floating-Point Matrix Multiplication on FPGAs. 204 - Maximilian Jakob Heer, José Quevedo, Marwan F. Abdelatti, Resit Sendag, Manbir Sodhi:
Efficient Implementation of a Genetic Algorithm for the Capacitated Vehicle Routing Problem on a High-Performance FPGA. 205 - Haodong Lu, Qichang Mei, Kun Wang:
An Efficient Piecewise Linear Approximation of Non-linear Operations for Transformer Inference. 206 - Prithviraj Yuvaraj, Amin Akalantar, Eamonn J. Keogh, Philip Brisk:
Feature Extraction Accelerator for Streaming Time Series. 207 - Yuan Dai
UPTRA: An Ultra-Parameterized Temporal CGRA Modeling and Optimization. 208 - Christian Maximilian Karle, Marc Neu
ReLoDAQ: Resource-Efficient, Low-Overhead 200 Gbits-1 Data Acquisition System for 6G Prototyping. 209 - Zainab Aizaz
FASBM: FPGA-specific Approximate Sum-based Booth multipliers for energy efficient Hardware Acceleration of Image Processing and Machine Learning Applications. 210 - Gong-Lang Zhou, Kaiyuan Guo, Xiang Chen, Kwok Wa Leung:
SpCNA: An FPGA-based Accelerator for Point Cloud Convolutional Neural Networks. 211 - Anna Drewes, Vitalii Burtsev, Bala Gurumurthy, Martin Wilhelm, David Broneske, Gunter Saake, Thilo Pionteck:
A Flexible and Scalable Reconfigurable FPGA Overlay Architecture for Data-Flow Processing. 212 - Antonio Filgueras, Miquel Vidal
Improving Performance of HPC Kernels on FPGAs Using High-Level Resource Management. 213 - James Bickerstaff, Luke Kljucaric
Accelerating Graph Analytics with oneAPI and Intel FPGAs. 214 - Thiem Van Chu, Yu Mizutani, Yuta Nagahara, Shungo Kumazawa, Kazushi Kawamura, Jaehoon Yu, Masato Motomura:
Decision Forest Training Accelerator Based on Binary Feature Decomposition. 215 - José Oliver, Carlos Álvarez
b8c: SpMV accelerator implementation leveraging high memory bandwidth. 216 - Namitha Liyanage
Scalable Quantum Error Correction for Surface Codes using FPGA. 217 - Sige Bian, He Li, Chengcheng Wang, Changjun Song, Yongming Tang:
MSBF-LSTM: Most-significant Bit-first LSTM Accelerators with Energy Efficiency Optimisations. 218 - Thijs Havinga, Xianjun Jiao, Wei Liu, Ingrid Moerman:
Accelerating FPGA-Based Wi-Fi Transceiver Design and Prototyping by High-Level Synthesis. 219 - Robert Szafarczyk, Syed Waqar Nabi, Wim Vanderbauwhede:
Dynamically Scheduled Memory Operations in Static High-Level Synthesis. 220 - Yueyin Bai, Hao Zhou, Keqing Zhao, Jianli Chen, Jun Yu, Kun Wang:
Transformer-OPU: An FPGA-based Overlay Processor for Transformer Networks. 221 - Veronia Iskandar, Mohamed A. Abd El Ghany, Diana Goehringer
Compiler-Assisted Kernel Selection for FPGA-based Near-Memory Computing Platforms. 222 - Luke Kljucaric
Clustering Classification on FPGAs for Neuromorphic Feature Extraction. 223 - M. D. Arafat Kabir, Joshua Hollis, Atiyehsadat Panahi, Jason D. Bakos, Miaoqing Huang, David Andrews:
Making BRAMs Compute: Creating Scalable Computational Memory Fabric Overlays. 224 - Sanjay Gandham, Lingxiang Yin, Hao Zheng, Mingjie Lin:
OCMGen: Extended Design Space Exploration with Efficient FPGA Memory Inference. 225 - Bingbing Peng, Shaoyang Sun, Yuan Dai
PRAD: A Bayesian Optimization-based DSE Framework for Parameterized Reconfigurable Architecture Design. 226 - Yuanfang Wang, Yu Li, Haoyang Zhang, Jun Yu, Kun Wang:
Moth: A Hardware Accelerator for Neural Radiance Field Inference on FPGA. 227 - Debjit Pal:
FCCM 2023 PhD Student Forum Compendium of Abstracts: Held on 9th May, 2023, at Los Angeles, USA. 228-229 - Andrew David Gunter
Reformulating the FPGA Routability Prediction Problem with Machine Learning. 230-232 - Hanqiu Chen, Cong Hao:
Hardware/Software Co-design for Machine Learning Accelerators. 233-235 - Rishov Sarkar
From Acceleration to Accelerating Acceleration: Modernizing the Accelerator Landscape using High-Level Synthesis. 236-238 - Vincent Meyers, Mehdi B. Tahoori:
Power Side-Channel Attacks and Defenses for Neural Network Accelerators. 239-241 - Wenbin Teng, Lei Gong, Chao Wang, Xuehai Zhou:
Enabling Elastic Resource Management in Cloud FPGAs via A Multi-layer Collaborative Approach. 242-244 - Yi-Chien Lin, Viktor K. Prasanna:
A Framework for Graph Machine Learning on Heterogeneous Architecture. 245-246 - Zheyuan Zou, Lei Gong, Chao Wang, Xuehai Zhou:
DataMaster: A GNN-based Data Type Optimizer for Dataflow Design in FPGA. 247-249
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