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CODES+ISSS 2003: Newport Beach, CA, USA
- Rajesh Gupta, Yukihiro Nakamura, Alex Orailoglu, Pai H. Chou:
Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2003, Newport Beach, CA, USA, October 1-3, 2003. ACM 2003, ISBN 1-58113-742-7
Architectural exploration and system simulations
- Youngmin Yi, Dohyung Kim, Soonhoi Ha:
Virtual synchronization technique with OS modeling for fast and time-accurate cosimulation. 1-6 - Tim Kogel, Malte Doerper, Andreas Wieferink, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Serge Goossens:
A modular simulation framework for architectural exploration of on-chip interconnection networks. 7-12 - Mehrdad Reshadi, Nikhil Bansal, Prabhat Mishra
, Nikil D. Dutt
An efficient retargetable framework for instruction-set simulation. 13-18
Advances in system modeling
- Lukai Cai, Daniel Gajski:
Transaction level modeling: an overview. 19-24 - Eike Grimpe, Frank Oppenheimer:
Extending the SystemC synthesis subset by object-oriented features. 25-30 - Haobo Yu, Andreas Gerstlauer, Daniel Gajski:
RTOS scheduling in transaction level models. 31-36 - Shaojie Wang, Sharad Malik
Synthesizing operating system based device drivers in embedded systems. 37-44
Support for real time and OS services in embedded systems
- Paul Kohout, Brinda Ganesh, Bruce L. Jacob:
Hardware support for real-time operating systems. 45-51 - Feng Zhao, Jie Liu, Jim Reich, Maurice Chu, Juan Liu:
Programming embedded networked sensor systems. 52
Case studies in embedded systems
- Wei Ming Lim, Mohammed Benaissa:
Design space exploration of a hardware-software co-designed GF(2m) galois field processor for forward error correction and cryptography. 53-58 - Arezou Koohi, Nader Bagherzadeh, Chengzi Pan:
A fast parallel reed-solomon decoder on a reconfigurable architecture. 59-64 - Andreas Hagen, Daniel A. Connors, Bryan L. Pellom:
The analysis and design of architecture systems for speech recognition on modern handheld-computing devices. 65-70
Invited session A
- Raul Camposano, Mark Underseth, Faraydon Karim:
Industry best practices in embedded software. 72-73
Invited session B
- Doug Burger:
Architectural versus physical solutions for on-chip communication challenges. 74 - Luca P. Carloni, Alberto L. Sangiovanni-Vincentelli:
On-chip communication design: roadblocks and avenues. 75-76 - Jason Cong, Yiping Fan, Guoling Han, Xun Yang, Zhiru Zhang:
Architecture and synthesis for multi-cycle on-chip communication. 77-78 - Reinaldo A. Bergamaschi, Grant Martin:
System-level design tools: who needs them, who has them, and how much should they cost? 79-80 - Mojy C. Chian:
Driving forces behind SOC development. 81 - Nikil D. Dutt
Driving agenda for systems research. 82
System modeling
- Traian Pop, Petru Eles, Zebo Peng:
Design optimization of mixed time/event-triggered distributed embedded systems. 83-89 - Todor P. Stefanov, Ed F. Deprettere:
Deriving process networks from weakly dynamic applications in system-level design. 90-96
System modeling
- Rafael Peset Llopis, Ramanathan Sethuraman, Carlos A. Alba Pinto, Harm Peters, Steffen Maul, Marcel Oosterhuis:
A low-cost and low-power multi-standard video encoder. 97-102
Case studies
- Behzad Mohebbi, Eliseu Chavez Filho, Rafael Maestre
A case study of mapping a software-defined radio (SDR) application on a reconfigurable DSP core. 103-108 - Roman L. Lysecky, Frank Vahid:
A codesigned on-chip logic minimizer. 109-113
Advances in embedded software scheduling techniques
- Pao-Ann Hsiung, Cheng-Yi Lin:
Synthesis of real-time embedded software with local and global deadlines. 114-119 - Peng Yang, Francky Catthoor:
Pareto-optimization-based run-time task scheduling for embedded systems. 120-125 - N. Ranganathan, Ashok K. Murugavel:
A low power scheduler using game theory. 126-131
Architectural design for embedded systems
- Ananth Hegde, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin:
VL-CDRAM: variable line sized cached DRAMs. 132-137 - Chanik Park, Jaeyu Seo, Sunghwan Bae, Hyojun Kim, Shinhan Kim, Bumsoo Kim:
A low-cost memory architecture with NAND XIP for mobile embedded systems. 138-143 - Qingfeng Zhuge, Zili Shao
Design space minimization with timing and code size optimization for embedded DSP. 144-149
Work-in-progress session on innovative topics
- Reinaldo A. Bergamaschi, Youngsoo Shin, Nagu R. Dhanwada, Subhrajit Bhattacharya, William E. Dougherty, Indira Nair, John A. Darringer, Sarala Paliwal:
SEAS: a system for early analysis of SoCs. 150-155 - JoAnn M. Paul:
Programmers' views of SoCs. 156-181 - Catherine H. Gebotys, Y. Zhang:
Security wrappers and power analysis for SoC technologies. 162-167 - Susan Cotterell, Frank Vahid, Walid A. Najjar, Harry Hsieh:
First results with eBlocks: embedded systems building blocks. 168-175
Verification, analysis of embedded systems
- Tarvo Raudvere, Ingo Sander, Ashish Kumar Singh, Axel Jantsch:
Verification of design decisions in ForSyDe. 176-181 - Cagkan Erbas, Selin C. Erbas, Andy D. Pimentel:
A multiobjective optimization model for exploring multiprocessor mappings of process networks. 182-187 - Heiko Zimmer, Axel Jantsch:
A fault model notation and error-control scheme for switch-to-switch buses in a network-on-chip. 188-193 - James Lin:
Design technology challenges for system and chip level designs in very deep submicron technologies. 194
Performance estimation in system design
- Sungchan Kim, Chaeseok Im, Soonhoi Ha:
Schedule-aware performance estimation of communication architecture for efficient design space exploration. 195-200 - Hemendra Singh Negi, Tulika Mitra
Accurate estimation of cache-related preemption delay. 201-206 - William Fornaciari
Early estimation of the size of VHDL projects. 207-212
Compiler optimizations for power, performance
- Guangyu Chen, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Mario Wolczko:
Tracking object life cycle for leakage energy optimization. 213-218 - Björn Franke
Compiler parallelization of C programs for multi-core DSPs with multiple address spaces. 219-224 - Haiyong Xie, Li Zhao, Laxmi N. Bhuyan:
Architectural analysis and instruction-set optimization for design of network protocol processors. 225-230 - Reinaldo A. Bergamaschi, Grant Martin, Wayne H. Wolf, Rolf Ernst, Kees A. Vissers, Jack Kouloheris:
The future of system-level design: can we find the right solutions to the right problems at the right time? 231
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