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A-SSCC 2020: Virtual Event, Japan
- IEEE Asian Solid-State Circuits Conference, A-SSCC 2020, Virtual Event, Japan, November 9-11, 2020. IEEE 2020, ISBN 978-1-7281-8436-4
- Chendi Yu, Howard C. Luong:
An 8-mW 66-GHz Active Circulator with 40dB TX-RX Isolation in 65nm CMOS for Full-Duplex Radios. 1-4 - Unbong Lee, Doojin Jang, Wanyeong Jung, Minkyu Je:
Input-Adaptive and Regulated Multi-Output Power Management Unit for Wireless Power Reception and Distribution in Multi-Unit Implantable Devices. 1-4 - Koji Yoichi, Sugako Otani, Kazutoshi Tsuda, Naoya Tokimoto, Hideki Kamegawa, Yoshihisa Satou, Shioto Tanaka, Hideki Otsu, Mitsuru Hiraki, Masao Ito, Mitsuya Fukazawa, Hiroyuki Kondo:
A High-Precision Analog Front End Integrated in a 32bit Microcontroller for Industrial Sensing Applications. 1-4 - Kang-Il Cho, Ho-Jin Kim, Jun-Ho Boo, Yong-Sik Kwak, Jun-Sang Park, Seung-Hoon Lee, Gil-Cho Ahn:
A 10-b 900-MS/s Single-Channel Pipelined-SAR ADC Using Current-Mode Reference Scaling. 1-2 - Yue Yin, Syed Muhammad Abubakar, Songyao Tan, Hanjun Jiang, Zhihua Wang, Seng-Pan U, Wen Jia:
A 17.7-pJ/Cycle ECG Processor for Arrhythmia Detection with High Immunity to Power Line Interference and Baseline Drift. 1-4 - Cheng-Ze Shao
, Yu-Te Liao
A 950-pW, 39-pJ/Conversion Leakage-Based Temperature-to-Digital Converter With 43mk Resolution. 1-4 - Liheng Liu, Yanlong Zhang
A Power Efficient ECG Front-End with Input-Adaptive Gain Reaching 67.6-dB Dynamic Range. 1-4 - Xin Xin, Linxiao Shen, Xiyuan Tang, Yi Shen, Jueping Cai, Nan Sun:
A Power-Efficient 13-Tap FIR filter and an IIR Filter Embedded in a 10-bit SAR ADC. 1-4 - Hao-Yun Lee, Peng-Wei Huang, Ding-Siang Ciou, Zhan-Xian Liao, Shuenn-Yuh Lee:
A Power-Efficient Current Readout Circuit with VCO-Based 2nd-Order CT ΔΣ ADC for Electrochemistry Acquisition. 1-2 - Pranith R. Byreddy
287-GHz CMOS Transceiver Pixel Array in a QFN Package for Active Imaging. 1-4 - Jun-Yeol Lee, Hye-Ran Kim, Sanghyeon Park, Jung-Hoon Chun:
A Dual-Mode Ground-Referenced Signaling Transceiver with a 3-Tap Feed-Forward Equalizer for Memory Interfaces. 1-4 - Shilei Hao, Yiwu Tang, Xuan Ding
An 8.3% Efficiency 96-134 GHz CMOS Frequency Doubler Using Distributed Amplifier and Nonlinear Transmission Line. 1-2 - Wenyu Sun, Chen Tang, Zhuqing Yuan, Zhe Yuan, Huazhong Yang, Yongpan Liu:
A 112-765 GOPS/W FPGA-based CNN Accelerator using Importance Map Guided Adaptive Activation Sparsification for Pix2pix Applications. 1-4 - Jeongsup Lee, Yejoong Kim, Minchang Cho, Makoto Yasuda, Satoru Miyoshi, Masaru Kawaminami, David T. Blaauw, Dennis Sylvester:
AµProcessor Layer for mm-Scale Die-Stacked Sensing Platforms Featuring Ultra-Low Power Sleep Mode at 125°C. 1-4 - Wei Tsao, Da Sun, Chunlei Fan, Kuohsin Chen, Yingte Wang:
Co-optimization targeting future interconnection. 1-4 - Giannino Dziallas, Adel Fatemi
A Monolithically Integrated Optical Bandpass Receiver in 0.25µm SiGe BiCMOS Technology for Microwave-Photonic Applications. 1-4 - Sung-Hao Wang
Improved Design and In Vivo Animal Tests of Bone-Guided Cochlear Implant Microsystem with Monopolar Biphasic Multiple Stimulation and Neural Action Potential Acquisition. 1-4 - Jianming Zhao, Yuan Gao
A 0.5-to-1.2V, 310nA Quiescent Current, 3fs-FoM Time-Domain Output-Capacitorless LDO with Propagation-Delay-Triggered Edge Detector. 1-2 - Yu-Chin Hsu, Robert Chen-Hao Chang
Intelligent Chips and Technologies for AIoT Era. 1-4 - Aminah Hina, Wala Saadeh
A 186µW Glucose Monitoring SoC using Near-Infrared Photoplethysmography. 1-4 - Zhan-Xian Liao, Yao-Tse Chang, Chieh Tsou, Po-Hao Cheng, Hao-Yun Lee, Peng-Wei Huang, Shuenn-Yuh Lee, Chou-Ching K. Lin, Gia-Shing Shieh:
Wireless Charging EEG Monitoring SoC with AI Algorithm-driven Electrical and Optogenetic Stimulation for Epilepsy Control. 1-2 - Toshiyuki Shimizu:
Supercomputer Fugaku: Co-designed with application developers/researchers. 1-4 - Soyeon Kim, Sanghoon Kang, Donghyeon Han, Sangyeob Kim, Sangjin Kim, Hoi-Jun Yoo:
An Energy-Efficient GAN Accelerator with On-chip Training for Domain Specific Optimization. 1-4 - Jie Lin, Chenchang Zhan, Yan Lu:
A 6.78-MHz Single-Stage Regulating Rectifier with Hysteretic Control and Current-Wave Modulation. 1-2 - Shota Konno
A 16b 1.62MS/s Calibration-free SAR ADC with 86.6dB SNDR utilizing DAC Mismatch Cancellation Based on Symmetry. 1-2 - Jinq Horng Teo, K. Ali, Massimo Alioto:
Voice Activity Detection with >83% Accuracy under SNR down to -3dB at $1.19\mu \mathrm{W}$ and 0.07mm2 in 40nm. 1-3 - Jianming Zhao, Yuan Gao
A 8-channel Rectifier-Free SECE Circuit with 15nA/ch Quescient Current and 580% Efficiency Improvement for Ambient Vibration Energy Harvesting with Broadband MEMS PET Array. 1-2 - Yu-Ting Lin, Wei-Zen Chen:
A 50 Gb/s PAM-4 Transmitter with Feedforward Equalizer and Background Phase Error Calibration. 1-2 - Jiajun Wu, Xuan Huang, Le Yang, Liang Wang, Jipeng Wang
An Energy-efficient Multi-core Restricted Boltzmann Machine Processor with On-chip Bio-plausible Learning and Reconfigurable Sparsity. 1-4 - Takanori Isono, Makoto Yamakura, Satoshi Shimaya, Isao Kawamoto, Nobuhiro Tsuboi, Masaaki Mineo, Wataru Nakajima, Kenichi Ishida, Shin Sasaki, Toshio Higuchi, Masahiro Hoshaku, Daisuke Murakami, Toshifumi Iwasaki, Hiroshi Hirai:
A 12.1 TOPS/W Mixed-precision Quantized Deep Convolutional Neural Network Accelerator for Low Power on Edge / Endpoint Device. 1-4 - Dewei Wang, Pavan Kumar Chundi, Sung Justin Kim, Minhao Yang, Joao Pedro Cerqueira, Joonsung Kang, Seungchul Jung, Sang Joon Kim, Mingoo Seok:
Always-On, Sub-300-nW, Event-Driven Spiking Neural Network based on Spike-Driven Clock-Generation and Clock- and Power-Gating for an Ultra-Low-Power Intelligent Device. 1-4 - Kyung-Sik Choi, Keun-Mok Kim, Jinho Ko, Sang-Gug Lee:
A 5 dBm 30.6% Efficiency 915 MHz Transmitter with 210 μW ULP PLL Employing Frequency Tripler and Digitally Controlled Duty/Phase Calibration Buffer. 1-4 - Vishnu P. Nambiar, Junran Pu, Yun Kwan Lee, Aarthy Mani, Tao Luo
0.5V 4.8 pJ/SOP 0.93µW Leakage/core Neuromorphic Processor with Asynchronous NoC and Reconfigurable LIF Neuron. 1-4 - Jaekwon Kim, Youngjun Ko, Jahoon Jin
A Jitter-Tolerant Referenceless Digital-CDR for Cellular Transceivers. 1-4 - Jaekwang Yun
A 0.4-1.7GHz Wide Range Fractional-N PLL Using a Transition-Detection DAC for Jitter Reduction. 1-4 - Jianxun Yang, Yuyao Kong, Zhao Zhang, Zhuangzhi Liu, Jing Zhou, Yiqi Wang, Yonggang Liu, Chenfu Guo, Te Hu, Congcong Li, Leibo Liu, Jin Zhang, Shaojun Wei, Jun Yang, Shouyi Yin:
A Time-Domain Computing-in-Memory based Processor using Predictable Decomposed Convolution for Arbitrary Quantized DNNs. 1-4 - Jun-Sang Park, Je-Min Jeon, Jun-Ho Boo, Jae-Hyuk Lee, Kang-Il Cho, Ho-Jin Kim, Gil-Cho Ahn, Seung-Hoon Lee:
A 2.2mW 12-bit 200MS/s 28nm CMOS Pipelined SAR ADC with Dynamic Register-Based High-Speed SAR Logic. 1-2 - Zexi Ji, Wanyeong Jung
CompAcc: Efficient Hardware Realization for Processing Compressed Neural Networks Using Accumulator Arrays. 1-4 - Gunjan Mandal, Sunil Rajan, Sanjeeb Kumar Ghosh, Saikat Hazra, Raghavendra Molthati, Parin Rajnikant Bhuta, Santosh Kumar Reddy, Vishnu Kalyanamahadevi Gopalan Jawarlal, Sumanth Chakkirala, Avneesh Singh Verma, Umamaheswara Reddy Katta, Venugopal Sadana, Dayakar Bethi, Abul Hassan Savanur, Praveen S. Bharadwaj, Krupal Jitendra Mehta, Kuntal Pandya:
A 2.68mW/Gbps, 1.62-8.1Gb/s Receiver for Embedded DisplayPort Version1.4b to Support 14dB Channel Loss. 1-4 - Jiawei Xu, Zhiliang Hong:
A 2-Electrode ECG Amplifier with 0.5% Nominal Gain Shift and 0.13% THD in a 530mVpp Input Common-Mode Range. 1-4 - Hung-Chih Liu, Hsun-Wei Chan, Henry Lopez Davila
A 16/64 QAM Baseband SoC for mm-Wave Transceiver with Self-Healing for FD/FI IQ Mismatch, LO Leakage and CFO/SCO/PNC. 1-2
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