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ASAP 2014: Zurich, Switzerland
- IEEE 25th International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2014, Zurich, Switzerland, June 18-20, 2014. IEEE Computer Society 2014, ISBN 978-1-4799-3609-0
Session 1: Hardware Accelerators I
- Kubilay Atasu
:
Resource-efficient regular expression matching architecture for text analytics. 1-8 - Yuk-Ming Choi, Hayden Kwok-Hay So
Map-reduce processing of k-means algorithm with FPGA-accelerated computer cluster. 9-16 - Iñaki Bildosola
Adaptive scalable SVD unit for fast processing of large LSE problems. 17-24 - Michael Gautschi, Michael Muehlberghuber, Andreas Traber, Sven Stucki, Matthias Baer, Renzo Andri, Luca Benini
SIR10US: A tightly coupled elliptic-curve cryptography co-processor for the OpenRISC. 25-29 - Mohammad Badawi, Ahmed Hemani, Zhonghai Lu:
Customizable coarse-grained energy-efficient reconfigurable packet processing architecture. 30-35 - Stewart Denholm, Hiroaki Inoue, Takashi Takenaka, Tobias Becker
Low latency FPGA acceleration of market data feed arbitration. 36-40
Session 2: Computer Arithmetic
- Florent de Dinechin, Matei Istoan, Abdelbassat Massouri:
Sum-of-product architectures computing just right. 41-47 - Hamad Alrimeih, Daler N. Rakhmatov:
Pipelined modular multiplier supporting multiple standard prime fields. 48-56 - Karim Bigou
RNS modular multiplication through reduced base extensions. 57-62 - Mioara Joldes, Jean-Michel Muller
On the computation of the reciprocal of floating point expansions using an adapted Newton-Raphson iteration. 63-67
Poster Session I
- Amro Altamimi, Daler N. Rakhmatov, Michael McGuire:
Polar baseband receiver for low-end WLAN. 68-69 - Yun-Nan Chang, Ting-Chi Tong:
Design of a 2D graphics front-end rendering processor. 70-71 - Michael J. Hall
Performance modeling of virtualized custom logic computations. 72-73 - Ali Hayek, Bashier Machmur, Michael Schreiber, Josef Börcsök, Stefan Golz, Mario Epp:
HICore1: "Safety on a chip" turnkey solution for industrial control. 74-75 - Mehdi Modarressi, Hamid Sarbazi-Azad:
A reconfigurable network-on-chip architecture for heterogeneous CMPs in the dark-silicon era. 76-77 - Simon Pontie, Paolo Maistri:
Randomized windows for secure scalar multiplication on elliptic curves. 78-79 - Mariagiovanna Sami, Gianluca Palermo
Virtual semi-concurrent self-checking for heterogeneous MPSoC architectures. 80-81 - Hao Xiao, Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda, Guanyu Zhu:
Distributed synchronization for message-passing based embedded multiprocessors. 82-83
Session 3: Performance and Power Analysis
- Lin Ma, Roger D. Chamberlain, Kunal Agrawal:
Performance modeling for highly-threaded many-core GPUs. 84-91 - Heiner Giefers
Analyzing the energy-efficiency of dense linear algebra kernels by power-profiling a hybrid CPU/FPGA system. 92-99 - Nathaniel A. Conos, Saro Meguerdichian, Miodrag Potkonjak:
Coordinated and adaptive power gating and dynamic voltage scaling for energy minimization. 100-107 - Ahmad Lashgar
A case against small data types in GPGPUs. 108-113
Session 4: Architectures I
- Francesco Conti
He-P2012: Architectural heterogeneity exploration on a scalable many-core platform. 114-120 - Hamed Tabkhi, Robert Bushey, Gunar Schirner:
Function-Level Processor (FLP): Raising efficiency by operating at function granularity for market-oriented MPSoC. 121-130 - Waqar Hussain
Design of an accelerator-rich architecture by integrating multiple heterogeneous coarse grain reconfigurable arrays over a network-on-chip. 131-138 - Ruan de Clercq, Frank Piessens, Dries Schellekens, Ingrid Verbauwhede
Secure interrupts on low-end microcontrollers. 147-152
Session5: Programming Regular Papers
- Konstantinos Krommydas, Wu-chun Feng, Muhsen Owaida, Christos D. Antonopoulos
On the characterization of OpenCL dwarfs on fixed and reconfigurable platforms. 153-160 - Edoardo Paone, Davide Gadioli, Gianluca Palermo
Evaluating orthogonality between application auto-tuning and run-time resource management for adaptive OpenCL applications. 161-168 - Thomas Peyret
Efficient application mapping on CGRAs based on backward simultaneous scheduling/binding and dynamic graph transformations. 169-172 - Moritz Schmid, Alexandru Tanase, Frank Hannig
Domain-specific augmentations for High-Level Synthesis. 173-177
Poster Session 2
- Junyi Han, Robert Haines, Adel Salhli, John Martin Brooke, Bruce D'Amora, Bob Danani:
Virtual science on the move: Interactive access to simulations on supercomputers. 178-179 - Keerthan Jaic, Melissa C. Smith, Nilim Sarma:
A practical network intrusion detection system for inline FPGAs on 10GbE network adapters. 180-181 - Yanhua Li, Youhui Zhang, Jianfeng Yang, Wayne Luk, Guangwen Yang, Weimin Zheng:
An approach of processor core customization for stencil computation. 182-183 - Yongchao Liu
SWAPHI: Smith-waterman protein database search on Xeon Phi coprocessors. 184-185 - Kevin Shen-Hoong Ong, Suhaib A. Fahmy
A scalable and compact systolic architecture for linear solvers. 186-187 - Zoltán Endre Rákossy, Farhad Merchant
Efficient and scalable CGRA-based implementation of Column-wise Givens Rotation. 188-189 - Tomohiro Ueno
Bandwidth compression of multiple numerical data streams for high performance custom computing. 190-191 - Shizhen Xu, Xiaomeng Huang, Yan Zhang, Yong Hu, Guangwen Yang:
A customized GPU acceleration of the princeton ocean model. 192-193
Session 6: Hardware Accelerators II
- Ce Guo, Wayne Luk, Stephen Weston:
Pipelined reconfigurable accelerator for ordinal pattern encoding. 194-201 - Janarbek Matai, Joo-Young Kim, Ryan Kastner
Energy efficient canonical huffman encoding. 202-209 - Zhenzhi Wu, Dake Liu:
Flexible multistandard FEC processor design with ASIP methodology. 210-218 - Kevin Cushon
Energy-efficient gear-shift LDPC decoders. 219-223
Session7: Memory Regular Papers
- Christian Pinto, Luca Benini
Exploring DMA-assisted prefetching strategies for software caches on multicore clusters. 224-231 - Majid Jalili, Hamid Sarbazi-Azad:
A compression-based morphable PCM architecture for improving resistance drift tolerance. 232-239
Session 8: Architectures II
- Tassadaq Hussain, Oscar Palomar
PVMC: Programmable Vector Memory Controller. 240-247 - Berkin Akin, Franz Franchetti, James C. Hoe:
Understanding the design space of DRAM-optimized hardware FFT accelerators. 248-255 - Deepak Gangadharan
Quality-aware video decoding on thermally-constrained MPSoC platforms. 256-263 - João Andrade, Frederico Pratas, Gabriel Falcão
Combining flexibility with low power: Dataflow and wide-pipeline LDPC decoding engines in the Gbit/s era. 264-269
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