default search action
ASAP 2013: Washington, DC, USA
- 24th International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2013, Washington, DC, USA, June 5-7, 2013. IEEE Computer Society 2013, ISBN 978-1-4799-0494-5
- Reiner W. Hartenstein:
The tunnel vision syndrome: Massively delaying progress. 1 - Roozbeh Jafari:
Wireless health: Challenges and opportunities. 1 - Hong Jiang:
An application-aware approach to systems support for big data. 1 - Josep Torrellas:
Extreme scale computer architecture: Energy efficiency from the ground up. 1 - Sun-Yuan Kung:
From green computing to big-data learning: A kernel learning perspective. 1 - Jürgen Teich, Alexandru Tanase, Frank Hannig
:
Symbolic parallelization of loop programs for massively parallel processor arrays. 1-9 - Srinivas Boppu, Frank Hannig
Loop program mapping and compact code generation for programmable hardware accelerators. 10-17 - Paul Grigoras, Xinyu Niu, José Gabriel F. Coutinho, Wayne Luk, Jacob A. Bower, Oliver Pell:
Aspect driven compilation for dataflow designs. 18-25 - Kavya Shagrithaya, Krzysztof Kepa
Enabling development of OpenCL applications on FPGA platforms. 26-30 - Alok Prakash, Siew Kei Lam, Thambipillai Srikanthan, Christopher T. Clarke:
Modelling communication overhead for accessing local memories in hardware accelerators. 31-34 - Gang Chen, Kai Huang, Jia Huang, Alois C. Knoll
Cache partitioning and scheduling for energy optimization of real-time MPSoCs. 35-41 - Ce Guo, Wayne Luk:
Accelerating HAC estimation for multivariate time series. 42-49 - Hyungman Park, Andreas Gerstlauer:
Toward a fast stochastic simulation processor for biochemical reaction networks. 50-58 - Kanak Agarwal, Raphael Polig:
A high-speed and large-scale dictionary matching engine for Information Extraction systems. 59-66 - Tobias Schneider, Ingo von Maurich, Tim Güneysu
Efficient implementation of cryptographic primitives on the GA144 multi-core architecture. 67-74 - Geng Zheng, Saraju P. Mohanty, Elias Kougianos, Oghenekarho Okobiah:
iVAMS: Intelligent metamodel-integrated Verilog-AMS for circuit-accurate system-level mixed-signal design exploration. 75-78 - Paul Wettin, Partha Pratim Pande, Deuk Hyoun Heo, Benjamin Belzer, Sujay Deb
Design space exploration for reliable mm-wave wireless NoC architectures. 79-82 - Keni Qiu, Mengying Zhao, Chenchen Fu, Liang Shi, Chun Jason Xue
Migration-aware loop retiming for STT-RAM based hybrid cache for embedded systems. 83-86 - Gabriel Yessin, Lubomir Riha
Application-specific processors for web-browsing: An exploration and evaluation of the design space. 87-90 - Lu Hao, Greg Stitt:
Virtual finite-state-machine architectures for fast compilation and portability. 91-94 - Jihoon Kang, Yohan Ko, Jongwon Lee, Yongjoo Kim, Hwisoo So, Kyoungwoo Lee, Yunheung Paek:
Selective validations for efficient protections on Coarse-Grained Reconfigurable Architectures. 95-98 - Aaron Landy, Greg Stitt:
Pseudo-constant logic optimization. 99-102 - Andrew G. Schmidt, Matthew French:
Fast lossless image compression with Radiation Hardening by hardware/software co-design on platform FPGAs. 103-106 - Jie Tang, Chen Liu
OCP: Offload Co-Processor for energy efficiency in embedded mobile systems. 107-110 - Wei Zhang, Yiqiang Ding:
Standard deviation of CPI: A new metric to evaluate architectural time predictability. 111-112 - Arnault Ioualalen, Matthieu Martel:
Synthesizing accurate floating-point formulas. 113-116 - Mark G. Arnold, Caroline Collange:
The Denormal Logarithmic Number System. 117-124 - Pedro Miguens Matutino
A compact and scalable RNS architecture. 125-132 - George Razvan Voicu, Mihai Lefter, Marius Enachescu
3D stacked wide-operand adders: A case study. 133-141 - Edem Kwedzo Bankas, Kazeem Alagbe Gbolagade
An effective New CRT based reverse converter for a novel moduli set {22n+1 - 1, 22n+1, 22n - 1}. 142-146 - Jae Hong Min, Earl E. Swartzlander Jr.:
Fused floating-point two-term sum-of-squares unit. 147-152 - Mohammad Hossein Hajkazemi, Amirali Baniasadi, Hossein Asadi
FARHAD: A Fault-Tolerant Power-Aware Hybrid Adder for add intensive applications. 153-159 - John D. Cappello, Dave Strenski:
A practical measure of FPGA floating point acceleration for High Performance Computing. 160-167 - Yang Gao, Jason D. Bakos:
Sparse matrix-vector multiply on the Texas Instruments C6678 Digital Signal Processor. 168-174 - Ardavan Pedram, John D. McCalpin, Andreas Gerstlauer:
Transforming a linear algebra core to an FFT accelerator. 175-184 - Kevin Townsend, Joseph Zambreno:
Reduce, Reuse, Recycle (R3): A design methodology for Sparse Matrix Vector Multiplication on reconfigurable platforms. 185-191 - Seok Won Heo, Suk Joong Huh, Milos D. Ercegovac:
Power optimization of sum-of-products design for signal processing applications. 192-197 - Adam Page, Tinoosh Mohsenin:
An efficient & reconfigurable FPGA and ASIC implementation of a spectral Doppler ultrasound imaging system. 198-202 - M. Alexandre Carbon, Yves Lhuillier, Henri-Pierre Charles
Hardware acceleration for Just-In-Time compilation on heterogeneous embedded systems. 203-210 - Robert Kirchgessner, Alan D. George
Reconfigurable computing middleware for application portability and productivity. 211-218 - Khoa Dang Pham, Abhishek Kumar Jain
Microkernel hypervisor for a hybrid ARM-FPGA platform. 219-226 - Muhammad Adeel Tajammul, Syed M. A. H. Jafri, Ahmed Hemani, Juha Plosila
Private configuration environments (PCE) for efficient reconfiguration, in CGRAs. 227-236 - Patrick Cooke, Jeremy Fowers, Greg Stitt, Lee Hunt:
A comparison of correntropy-based feature tracking on FPGAs and GPUs. 237-240 - Nuno Neves
BioBlaze: Multi-core SIMD ASIP for DNA sequence alignment. 241-244 - Mickael Njiki, Abdelhafid Elouardi, Samir Bouaziz, Olivier Casula, Olivier Roy:
A real-time implementation of the Total Focusing Method for rapid and precise diagnostic in non destructive evaluation. 245-248 - Athanasios K. Grivas, Terrence S. T. Mak, Alex Yakovlev
Novel Multi-Layer Network Decomposition boosting acceleration of multi-core algorithms. 249-252 - Karlo Gusso Lenzi
On the performance of code block segmentation for LTE-advanced. 253-256 - Peng Li, David J. Lilja:
Accelerating the performance of stochastic encoding-based computations by sharing bits in consecutive bit streams. 257-260 - David Uliana, Krzysztof Kepa
FPGA-based HPC application design for non-experts. 261-264 - Vinh Q. Dang, Esam El-Araby
Accelerating nonlinear diffusion tensor estimation for medical image processing using high performance GPU clusters. 265-268 - Shashank Suresh, Spiridon F. Beldianu, Sotirios G. Ziavras
FPGA and ASIC square root designs for high performance and power efficiency. 269-272 - Sam Skalicky, Sonia López, Marcin Lukowiak, James Letendre, David Gasser:
Linear algebra computations in heterogeneous systems. 273-276 - Jamshaid Sarwar Malik, Ahmed Hemani, Nasirud Din Gohar:
Unifying CORDIC and Box-Muller algorithms: An accurate and efficient Gaussian Random Number generator. 277-280 - Christian Pinto, Luca Benini
A highly efficient, thread-safe software cache implementation for tightly-coupled multicore clusters. 281-288 - Junjun Gu, Gang Qu:
Incorporating temperature-leakage interdependency into dynamic voltage scaling for real-time systems. 289-296 - Wei Zhang, Yiqiang Ding:
Hybrid SPM-cache architectures to achieve high time predictability and performance. 297-304 - Hooman Jarollahi, Vincent Gripon, Naoya Onizawa, Warren J. Gross:
A low-power Content-Addressable Memory based on clustered-sparse networks. 305-308 - Simone Secchi, Marco Ceriani, Antonino Tumeo
Exploring hardware support for scaling irregular applications on multi-node multi-core architectures. 309-313 - Maxim Rykunov, Andrey Mokhov, Danil Sokolov, Alex Yakovlev
Design-for-adaptivity of microarchitectures. 314-320 - Li Tang
GPU acceleration of Data Assembly in Finite Element Methods and its energy implications. 321-328 - Da Li, Kittisak Sajjapongse, Huan Truong, Gavin C. Conant
A distributed CPU-GPU framework for pairwise alignments on large-scale sequence datasets. 329-338 - Waqar Hussain
A Reconfigurable Application-specific Instruction-set Processor for Fast Fourier Transform processing. 339-345 - Tao Yao, Deyuan Gao, Xiaoya Fan, Jari Nurmi
Correctly rounded architectures for Floating-Point multi-operand addition and dot-product computation. 346-355 - Aida Vosoughi, Guohui Wang, Hao Shen, Joseph R. Cavallaro
Highly scalable on-the-fly interleaved address generation for UMTS/HSPA+ parallel turbo decoder. 356-362 - Joshua S. Monson, Michael J. Wirthlin, Brad L. Hutchings:
Implementing high-performance, low-power FPGA-based optical flow accelerators in C. 363-369 - Stefan Craciun, Gongyu Wang, Alan D. George, Herman Lam, José C. Príncipe:
A scalable RC architecture for mean-shift clustering. 370-374
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-12-15 01:15 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: