default search action
NORCAS 2018: Tallinn, Estonia
- Jari Nurmi, Peeter Ellervee, Juri Mihhailov, Maksim Jenihhin, Kalle Tammemäe:
2018 IEEE Nordic Circuits and Systems Conference, NORCAS 2018: NORCHIP and International Symposium of System-on-Chip (SoC), Tallinn, Estonia, October 30-31, 2018. IEEE 2018, ISBN 978-1-5386-7656-1 - Imad ud Din, Stefan Andersson, Therese Forsberg, Henrik Sjöland
:
A 24GHz, 18dBm, Broadband, Three Stacked Power Amplifier in 28nm FDSOI. 1-4 - Elham Shamsa, Anil Kanduri, Amir M. Rahmani
Goal Formulation: Abstracting Dynamic Objectives for Efficient On-chip Resource Allocation. 1-4 - Mohammad Hassan Montaseri, Risto Vuohtoniemi, Janne Aikio
Design of Multi-Stacked CMOS mm-Wave Power Amplifiers for Phased Array Applications Using Triple-Well Process. 1-5 - Oliver Schrape, Alexey Balashov, Aleksandar Simevski, Carlos Benito
Master-Clone Placement with Individual Clock Tree Implementation - a Case on Physical Chip Design. 1-4 - Olaitan Olabode, Vishnu Unnikrishnan
A Configurable Hysteresis Comparator for Asynchronous Sigma-Delta Modulators. 1-4 - Martin Mosbeck, Daniel Hauer, Axel Jantsch
VELS: VHDL E-Learning System for Automatic Generation and Evaluation of Per-Student Randomized Assignments. 1-7 - Muhammad Fahim Ul Haque, Muhammad Touqir Pasha, Tahir Malik
A Comparison of Polar and Quadrature RF-PWM. 1-4 - Sajjad Nouri, Ramin Ghaznavi Youvalari
Design and Implementation of Multi-Purpose DCT/DST-Specific Accelerator on Heterogeneous Multicore Architecture. 1-10 - Dmitry Osipov, Steffen Paul:
Flying-Capacitor Bottom-Plate Sampling Scheme for Low-Power High-Resolution SAR ADCs. 1-4 - E. Ulvestad, Kristian Gjertsen Kjelgård
High-speed Sampling System in CMOS. 1-5 - Yang Yu, Elena Dubrova, Mats Näslund, Sha Tao:
On Designing PUF-Based TRNGs with Known Answer Tests. 1-6 - Hesam Zolfaghari, Davide Rossi, Jari Nurmi
Low-latency Packet Parsing in Software Defined Networks. 1-6 - Muhammad Obaidullah, Gul N. Khan
Multi-Swarm based NoC Configuration and Synthesis. 1-6 - Morten B. Petersen, Anthon V. Riber, Simon T. Andersen, Martin Schoeberl
Time-Predictable Distributed Shared Memory for Multi-Core Processors. 1-7 - Tapani Nevalainen, Esteban Ferro
Low-Power Regulator for Micro Energy Harvesting Applications. 1-5 - Markus Grozing, Johannes Digel, Thomas Veigel, Robert Bieg, Jianxiong Zhang, Simon Brandl, Martin Schmidt, Christoph Haslach, Daniel Markert, Wolfgang Templ:
A RF Pulse-Width and Pulse-Position Modulator IC in 28 nm FDSOI CMOS. 1-4 - Aram Baharmast
Noise Considerations in Pulse-Shaping Based TIA Channel Designed for a Pulsed TOF Laser Radar Receiver. 1-6 - Frank Herzel, Arzu Ergintav, Johannes Borngräber, Dietmar Kissinger:
A 15-50GHz Multiplexer Circuit in 130nm SiGe BiCMOS Technology for Ultra-Wide Frequency Ramps in FMCW Radar. 1-4 - Therese Forsberg, Johan Wernehag, Henrik Sjöland
A 4.3-mW mm-Wave Divide-by-Two Circuit with 30% Locking Range in 28-nm FD-SOI CMOS. 1-4 - Adele Maleki, Hamidreza Ahmadian, Roman Obermaisser:
Fault-Tolerant and Energy-Efficient Communication in Mixed-Criticality Networks-on-Chips. 1-7 - Reem W. Etman, Salma Hesham, Klaus Hoffman, Mohamed A. Abd El Ghany
Analysis of Synchronous-Asynchronous NoC for the Dark Silicon Era. 1-7 - T. Moradi Khanshan, K. G. Kjeldgard, E. Ulvestad, Dag T. Wisland, Tor Sverre Lande
CMOS photosensors for LIDAR. 1-5 - Eero Sankila, Veeti Kiuru, Janne Aikio
Building Lumped Models for Measured Passive mm-wave Components. 1-4 - Zhe Chen, Hao Gao, Peter G. M. Baltus:
A Design Approach for SiGe Low-Noise Amplifiers Using Wideband Input Matching. 1-4 - Yang Yu, Elena Dubrova, Mats Näslund, Sha Tao:
On Designing PUF-Based TRNGs with Known Answer Tests. 1-6 - Arjun Ramaswami Palaniappan, Liter Siek
A 0.0186 mm2, 0.65 V Supply, 9.53 ps RMS Jitter All-Digital PLL for Medical Implants. 1-4 - Mohammad Ali Pourabed, Sajjad Nouri, Jari Nurmi
Design and Implementation of 2D IDCT/IDST-Specific Accelerator on Heterogeneous Multicore Architecture. 1-6 - P. Ostrovsky, Oliver Schrape, Klaus Tittelbach-Helmrich, Frank Herzel, Gunter Fischer, D. Hellmann, P. Borner, A. Loose, P. Hartogh, Dietmar Kissinger:
A Radiation Hardened 16 GS/s Arbitrary Waveform Generator IC for a Submillimeter Wave Chirp-Transform Spectrometer. 1-4 - Mehdi Safarpour, Ilkka Hautala, Olli Silvén:
An Embedded Programmable Processor for Compressive Sensing Applications. 1-5 - Maksim Jenihhin
Towards Multidimensional Verification: Where Functional Meets Non-Functional. 1-7 - Jacob E. F. Overgaard, Jens Christian Hertel, Jens Pejtersen, Arnold Knott
Application Specific Integrated Gate-Drive Circuit for Driving Self-Oscillating Gallium Nitride & Logic-Level Power Transistors. 1-6 - Kim B. Ostman, Erlend Strandvik, Phil Corbishley, Tor Oyvind Vedal, Mika Salmi:
Analysis and Design of ESD Protection for Robust Low-Power Pierce Crystal Oscillator Startup. 1-4 - Victor Aberg
Design Considerations and Evaluation of a High-Speed SAR ADC. 1-6 - Jonas Stricker, Clemens Kain, Jérôme Kirscher, Andi Buzo
Semiconductor Component Fault Assessment and Probability Impact Estimation on Application Level. 1-4 - Vahur Kampus, Martin Trojer, Robert Teschner:
Unleashing the full power of feed-forward opamps: a 200MHz, fully differential, conditionally stable, 36dB gain PGA, using a four-stage multi-path 2.5V amplifier with double feed-forward compensation. 1-5 - Joonas Multanen, Heikki Kultala, Pekka Jääskeläinen
Energy-Delay Trade-Offs in Instruction Register File Design. 1-7 - Ayca Akkaya, Firat Celik, Armin Tajalli
A 10b SAR ADC with Widely Scalable Sampling Rate and AGC Amplifier Front-End. 1-6 - Christian Johansson, Torbjorn Manefjord:
Characterization and Considerations for Upset in FPGA. 1-4 - Kathy Hanley, Aidan Murphy, Niamh Creedon, Alan O'Riordan, Daniel O'Hare, Ivan John O'Connell:
Current Readout Circuit for Point-of-Care Infectious Disease Diagnostics in Animal Health. 1-5 - Nardi Utomo, Liter Siek
An 87% Peak Efficiency, 37W, Class H Audio Amplifier with GaN Output Stage. 1-6 - David Bierbuesse, Renato Negra:
Insertion-Loss Optimization of Transformer-based Matching Networks for mm-Wave Applications. 1-5 - David Lemma, Mehran Goli
Power Intent from Initial ESL Prototypes: Extracting Power Management Parameters*. 1-6 - Mustafa Kilic, Selman Ergünay, Yusuf Leblebici:
A Row-Column Accessed Dynamic Element Matching DAC Architecture for SAR ADCs. 1-5 - Somayeh Hossein Zadeh, Trond Ytterdal, Snorre Aunet:
Comparison of Ultra Low Power Full Adder Cells in 22 nm FDSOI Technology. 1-5 - Luis Cavo, Sebastien Fuhrmann, Liang Liu
Implementation of an Area Efficient Crypto Processor for a NB-IoT SoC Platform. 1-5 - Arun Jeevaraj, Emmanuel Laface, Maurizio Donna, Fredrik Edman, Liang Liu
FPGA Based Hybrid Computing Platform for ESS Linac Simulator. 1-4 - Mohammad Hassan Montaseri, Janne Aikio
Design of Stacked-MOS Transistor mm-Wave Class C Amplifiers for Doherty Power Amplifiers. 1-5 - Dennis Oland Larsen, Martin Vinter, Ivan H. H. Jørgensen:
Dynamically Reconfigurable Gearbox Switched-Capacitor DC-DC Converter. 1-5 - Ilia Kempi, Nouman Ahmed, Andreas Hammer, Olaitan Olabode, Vishnu Unnikrishnan
A Low-Power Hardware Stack for Continuous Data Streaming from Telemetry Implants. 1-6 - Ruei-Ting Chien, Yi-Lun Liao, Chien-An Wang, Yu-Cheng Li, Yi-Chang Lu
Three-Dimensional Dynamic Programming Accelerator for Multiple Sequence Alignment. 1-5 - Cesar G. Chaves
A Distributed DoS Detection Scheme for NoC-based MPSoCs. 1-6 - Jan Nissinen, Ilkka Nissinen
Time-gated CMOS SPAD and a Quantum Well Laser Diode with a CMOS Driver for Time-Resolved Diffuse Optics Imaging. 1-4 - Nicolai Behmann, Max Mehltretter
GPU-enhanced Multimodal Dense Matching. 1-6
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-11-15 19:19 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: