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MLCAD 2024: Salt Lake City, UT, USA
- Hussam Amrouch, Jiang Hu, Siddharth Garg, Yibo Lin:
Proceedings of the 2024 ACM/IEEE International Symposium on Machine Learning for CAD, MLCAD 2024, Salt Lake City, UT, USA, September 9-11, 2024. ACM 2024, ISBN 979-8-4007-0699-8 - Lizi Zhang
, Azadeh Davoodi
Efficient and Effective Neural Networks for Automatic Test Pattern Generation. 1:1-1:7 - Yunsheng Bai
Learning to Compare Hardware Designs for High-Level Synthesis. 2:1-2:7 - Jiajie Xu
FACT: Fast and Accurate Multi-Corner Predictor for Timing Closure in Commercial EDA Flows. 3:1-3:7 - Pinquan Li
ICDaIR: Distribution-aware Static IR Drop Prediction Flow Based on Image Classification. 4:1-4:6 - Ateeb Naseer
Enhancing the Capabilities of Quantum Transport Simulations Utilizing Machine Learning Strategies. 5:1-5:7 - Shiyu Gao
An ML-aided Approach to Automatically Generate Schematic Symbols in PCB EDA Tools. 6:1-6:7 - Wenjing Jiang
IR-Aware ECO Timing Optimization Using Reinforcement Learning. 7:1-7:7 - Rongjian Liang
ReLS: Retrieval Is Efficient Knowledge Transfer For Logic Synthesis. 8:1-8:7 - Yangfan Jiang
A Parallel Simulation Framework Incorporating Machine Learning-Based Hotspot Detection for Accelerated Power Grid Analysis. 9:1-9:7 - Christopher Batten
PyHDL-Eval: An LLM Evaluation Framework for Hardware Design Using Python-Embedded DSLs. 10:1-10:17 - Cristhian Roman-Vicharra
Flip-Flop Centric Incremental Placement for Simultaneous Timing and Clock Network Power Optimization. 11:1-11:7 - Haiyang He
Parallel Per-tile Activation with Linear Superposition of Thermal Response for Solving Arbitrary Power Pattern in 3DIC Thermal Simulation. 12:1-12:7 - Ruisi Zhang
Automated Physical Design Watermarking Leveraging Graph Neural Networks. 13:1-13:10 - Zongyue Qin
Cross-Modality Program Representation Learning for Electronic Design Automation with High-Level Synthesis. 14:1-14:12 - Kangwei Xu
Automated C/C++ Program Repair for High-Level Synthesis via Large Language Models. 15:1-15:9 - Ziqi Wang
High-Dimensional Yield Analysis Using Sparse Representation for Long-Tailed Distribution. 16:1-16:7 - Ruchao Fan
An Efficient ML-based Hardware Trojan Localization Framework for RTL Security Analysis. 17:1-17:7 - Ruidi Qiu
AutoBench: Automatic Testbench Generation and Evaluation Using LLMs for HDL Design. 18:1-18:10 - Donggyu Kim
TA3D: Timing-Aware 3D IC Partitioning and Placement by Optimizing the Critical Path. 19:1-19:7 - Bohao Li
Efficient Subgraph Matching Framework for Fast Subcircuit Identification. 20:1-20:7 - Amin Sarihi
TrojanForge: Generating Adversarial Hardware Trojan Examples Using Reinforcement Learning. 21:1-21:7 - Utsav Sharma
OpenROAD-Assistant: An Open-Source Large Language Model for Physical Design Tasks. 22:1-22:7 - Stefan Abi-Karam
HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond. 23:1-23:9 - Prianka Sengupta
MinBLoG: Minimization of Boolean Logic Functions using Graph Attention Network. 24:1-24:8 - Jincong Lu
Thermal Map Dataset for Commercial Multi/Many Core CPU/GPU/TPU. 25:1-25:7 - Andre Nakkab
Rome was Not Built in a Single Step: Hierarchical Prompting for LLM-based Chip Design. 26:1-26:11 - Tao Bai
Cell Library Characterization for Composite Current Source Models Based on Gaussian Process Regression and Active Learning. 27:1-27:7 - Prashanth Vijayaraghavan
Chain-of-Descriptions: Improving Code LLMs for VHDL Code Generation and Summarization. 28:1-28:10 - Avinash Ayalasomayajula
LASP: LLM Assisted Security Property Generation for SoC Verification. 29:1-29:7 - Xuanyi Tan
ML-TIME: ML-driven Timing Analysis of Integrated Circuits in the Presence of Process Variations and Aging Effects. 30:1-30:9 - Andrew David Gunter
Enabling Risk Management of Machine Learning Predictions for FPGA Routability. 31:1-31:9 - Andrew David Gunter
Machine Learning VLSI CAD Experiments Should Consider Atomic Data Groups. 32:1-32:8 - Ali Hammoud
Human Language to Analog Layout Using GLayout Layout Automation Framework. 33:1-33:7 - Haoyu Yang
Optimizing Predictive AI in Physical Design Flows with Mini Pixel Batch Gradient Descent. 34:1-34:7 - Luis Francisco
LLM Based Physical Verification Runset Generator. 35:1-35:7 - Lining Zhang, Baokang Peng, Yu Li, Hengyi Liu, Wu Dai, Runsheng Wang:
When Device Modeling Meets Machine Learning: Opportunities and Challenges (Invited). 36:1-36:6 - Srinivas Jallepalli
Machine Learning for High Sigma Analog Designs (Invited). 37:1-37:6 - Li-C. Wang
LLM-Assisted Analytics in Semiconductor Test (Invited). 38:1-38:7 - Michihiro Shintani
(Invited) Redefining Outliers for On-Wafer Electrical Testing. 39:1-39:7
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