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45th MICRO 2012: Vancouver, BC, Canada
- 45th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2012, Vancouver, BC, Canada, December 1-5, 2012. IEEE Computer Society 2012, ISBN 978-1-4673-4819-5
- Lei Jiang, Youtao Zhang, Bruce R. Childers, Jun Yang:
FPB: Fine-grained Power Budgeting to Improve Write Throughput of Multi-level Cell Phase Change Memory. 1-12 - Niladrish Chatterjee, Manjunath Shevgoor, Rajeev Balasubramonian, Al Davis, Zhen Fang, Ramesh Illikkal, Ravi R. Iyer:
Leveraging Heterogeneity in DRAM Main Memories to Accelerate Critical Word Access. 13-24 - Christian Jacobi, Timothy J. Slegel, Dan F. Greiner:
Transactional Memory Architecture and Implementation for IBM System Z. 25-36 - Hyeran Jeon, Murali Annavaram
:
Warped-DMR: Light-weight Error Detection for GPGPU. 37-47 - Damien Hardy, Isidoros Sideris, Nikolas Ladas, Yiannakis Sazeides:
The Performance Vulnerability of Architectural and Non-architectural Arrays to Permanent Faults. 48-59 - Andreas Prodromou, Andreas Panteli, Chrysostomos Nicopoulos
NoCAlert: An On-Line and Real-Time Fault Detection Mechanism for Network-on-Chip Architectures. 60-71 - Timothy G. Rogers
Cache-Conscious Wavefront Scheduling. 72-83 - Yongjun Park, Jason Jong Kyu Park, Hyunchul Park, Scott A. Mahlke:
Libra: Tailoring SIMD Execution Using Heterogeneous Hardware and Dynamic Configurability. 84-95 - Mark Gebhart, Stephen W. Keckler, Brucek Khailany, Ronny Krashinsky, William J. Dally:
Unifying Primary Cache, Scratch, and Register File Memories in a Throughput Processor. 96-106 - Haicheng Wu, Gregory Frederick Diamos, Srihari Cadambi, Sudhakar Yalamanchili:
Kernel Weaver: Automatically Fusing Database Primitives for Efficient GPU Computation. 107-118 - Daniel Wong
KnightShift: Scaling the Energy Proportionality Wall through Server-Level Heterogeneity. 119-130 - Krishna T. Malladi, Ian Shaeffer, Liji Gopalakrishnan, David Lo, Benjamin C. Lee, Mark Horowitz:
Rethinking DRAM Power Modes for Energy Proportionality. 131-142 - Qingyuan Deng, David Meisner, Abhishek Bhattacharjee, Thomas F. Wenisch, Ricardo Bianchini:
CoScale: Coordinating CPU and Memory System DVFS in Server Systems. 143-154 - Rustam Miftakhutdinov, Eiman Ebrahimi, Yale N. Patt:
Predicting Performance Impact of DVFS for Realistic Memory Systems. 155-165 - Timothy Hayes
Vector Extensions for Decision Support DBMS Acceleration. 166-176 - Pejman Lotfi-Kamran, Boris Grot
NOC-Out: Microarchitecting a Scale-Out Processor. 177-187 - Islam Atta, Pinar Tözün
SLICC: Self-Assembly of Instruction Cache Collectives for OLTP Workloads. 188-198 - Ramon Bertran
Systematic Energy Characterization of CMP/SMT Processor Systems via Automated Micro-Benchmarks. 199-211 - Youngtaek Kim, Lizy Kurian John, Sanjay Pant, Srilatha Manne, Michael J. Schulte, William Lloyd Bircher, Madhu Saravana Sibi Govindan:
AUDIT: Stress Testing the Automatic Way. 212-223 - Wei Huang, Charles Lefurgy, William Kuk, Alper Buyuktosunoglu, Michael S. Floyd, Karthick Rajamani, Malcolm Allen-Ware, Bishop Brock:
Accurate Fine-Grained Processor Power Proxies. 224-234 - Moinuddin K. Qureshi, Gabriel H. Loh:
Fundamental Latency Trade-off in Architecting DRAM Caches: Outperforming Impractical SRAM-Tags with a Simple and Practical Design. 235-246 - Jaewoong Sim, Gabriel H. Loh, Hyesoon Kim, Mike O'Connor
A Mostly-Clean DRAM Cache for Effective Hit Speculation and Self-Balancing Dispatch. 247-257 - Binh Pham, Viswanathan Vaidyanathan, Aamer Jaleel, Abhishek Bhattacharjee:
CoLT: Coalesced Large-Reach TLBs. 258-269 - Lizhong Chen, Timothy Mark Pinkston:
NoRD: Node-Router Decoupling for Effective Power-gating of On-Chip Routers. 270-281 - Randy Morris, Avinash Karanth Kodi, Ahmed Louri:
Dynamic Reconfiguration of 3D Photonic Networks-on-Chip for Maximizing Performance and Improving Fault Tolerance. 282-293 - Akbar Sharifi, Emre Kultursay, Mahmut T. Kandemir, Chita R. Das:
Addressing End-to-End Memory Access Latency in NoC-Based Multicores. 294-304 - Khubaib, M. Aater Suleman, Milad Hashemi, Chris Wilkerson, Yale N. Patt:
MorphCore: An Energy-Efficient Microarchitecture for High Performance ILP and High Throughput TLP. 305-316 - Andrew Lukefahr, Shruti Padmanabha, Reetuparna Das
Composite Cores: Pushing Heterogeneity Into a Core. 317-328 - Rami Sheikh, James Tuck, Eric Rotenberg:
Control-Flow Decoupling. 329-340 - Mohammad Alisafaee:
Spatiotemporal Coherence Tracking. 341-350 - Socrates Demetriades, Sangyeun Cho:
Predicting Coherence Communication by Tracking Synchronization Points at Run Time. 351-362 - Abdullah Muzahid, Shanxiang Qi, Josep Torrellas:
Vulcan: Hardware Support for Detecting Sequential Consistency Violations Dynamically. 363-375 - Snehasish Kumar, Hongzhou Zhao, Arrvindh Shriraman, Eric Matthews, Sandhya Dwarkadas
Amoeba-Cache: Adaptive Blocks for Eliminating Waste in the Memory Hierarchy. 376-388 - Nam Duong, Dali Zhao, Taesu Kim, Rosario Cammarota, Mateo Valero
Improving Cache Management Policies Using Dynamic Reuse Distances. 389-400 - Petar Radojkovic
Kernel Partitioning of Streaming Applications: A Statistical Approach to an NP-complete Problem. 401-412 - Weidan Wu, Benjamin C. Lee:
Inferred Models for Dynamic and Sparse Hardware-Software Spaces. 413-424 - Cheng Wang, Youfeng Wu, Hongbo Rong, Hyunchul Park:
SMARQ: Software-Managed Alias Register Queue for Dynamic Optimizations. 425-436 - Alain Ketterlin, Philippe Clauss
Profiling Data-Dependence to Assist Parallelization: Framework, Scope, and Optimization. 437-448 - Hadi Esmaeilzadeh, Adrian Sampson
Neural Acceleration for General-Purpose Approximate Programs. 449-460 - Jan van Lunteren, Christoph Hagleitner, Timothy Heil, Giora Biran, Uzi Shvadron, Kubilay Atasu
Designing a Programmable Wire-Speed Regular-Expression Matching Accelerator. 461-472
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