Summary
|
For Full-Text PDF, please login, if you are a member of IEICE, or go to Pay Per View on menu list, if you are a nonmember of IEICE. |
|
k Nearest Neighbor Classification Coprocessor with Weighted Clock-Mapping-Based Searching Fengwei AN Lei CHEN Toshinobu AKAZAWA Shogo YAMASAKI Hans Jürgen MATTAUSCH Publication IEICE TRANSACTIONS on Electronics Vol.E99-C No.3 pp.397-403 Publication Date: 2016/03/01 Online ISSN: 1745-1353 DOI: 10.1587/transele.E99.C.397 Type of Manuscript: PAPER Category: Electronic Circuits Keyword: k nearest neighbor classifier, minimal Euclidean distance search, clock-mapping concept, weighted frequency dividers, majority circuit, Full Text: PDF(974.5KB)>>
Summary: Nearest-neighbor-search classifiers are attractive but they have high intrinsic computational demands which limit their practical application. In this paper, we propose a coprocessor for k (k with k≥1) nearest neighbor (kNN) classification in which squared Euclidean distances (SEDs) are mapped into the clock domain for realizing high search speed and energy efficiency. The minimal SED searching is carried out by weighted frequency dividers that drastically reduce the normally exponential increase of the worst-case search-clock number with the bit width of vector components to only a linear increase. This also results in low power dissipation and high area-efficiency in comparison to the traditional method using large numbers of adders and comparators. The kNN classifier determines the class of an unknown input sample with a majority decision among the k nearest reference samples. The required majority-decision circuit is integrated with the clock-mapping-based minimal-SED searching architecture and proceeds with the classification immediately after identification of each of the k nearest references. A test chip in 180 nm CMOS technology, which can process 8 dimensions of 32 reference vectors in parallel, achieves low power dissipation of 40.32 mW (at 51.21 MHz clock frequency and 1.8 V supply voltage). Significantly, the distance search circuit consumes only 5.99 mW. Feature vectors with different dimensionality up to 2048 dimensions can be handled by the designed coprocessor due to a dimension extension circuit, enabling large flexibility for usage in different application. | |||||
|
|