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Multistage Function Speculation Adders Yinan SUN Yongpan LIU Zhibo WANG Huazhong YANG Publication IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Vol.E98-A No.4 pp.954-965 Publication Date: 2015/04/01 Online ISSN: 1745-1337 DOI: 10.1587/transfun.E98.A.954 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: multistage function speculation, variable latency adder, design methodology, Full Text: PDF(1.5MB)>>
Summary: Function speculation design with error recovery mechanisms is quite promising due to its high performance and low area overhead. Previous work has focused on two-stage function speculation and thus lacks a systematic way to address the challenge of the multistage function speculation approach. This paper proposes a multistage function speculation with adaptive predictors and applies it in a novel adder. We deduced the analytical performance and area models for the design and validated them in our experiments. Based on those models, a general methodology is presented to guide design optimization. Both analytical proofs and experimental results on the fabricated chips show that the proposed adder's delay and area have a logarithmic and linear relationship with its bit number, respectively. Compared with the DesignWare IP, the proposed adder provides the same performance with 6-17% area reduction under different bit lengths. | ||||||||||
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