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Co-simulation of On-Chip and On-Board AC Power Noise of CMOS Digital Circuits Kumpei YOSHIKAWA Yuta SASAKI Kouji ICHIKAWA Yoshiyuki SAITO Makoto NAGATA Publication IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Vol.E95-A No.12 pp.2284-2291 Publication Date: 2012/12/01 Online ISSN: 1745-1337 DOI: 10.1587/transfun.E95.A.2284 Print ISSN: 0916-8508 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Device and Circuit Modeling and Analysis Keyword: LSI chip-package-board co-design, electromagnetic compatibility, power supply noise, power delivery network, Full Text: PDF(2.3MB)>>
Summary: Capacitor charging modeling efficiently and accurately represents power consumption current of CMOS digital circuits and actualizes co-simulation of AC power noise including the interaction with on-chip and on-board integrated power delivery network (PDN). It is clearly demonstrated that the AC power noise is dominantly characterized by the frequency-dependent impedance of PDN and also by the operating frequency of circuits as well. A 65 nm CMOS chip exhibits the AC power noise components in substantial relation with the parallel resonance of the PDN seen from on-chip digital circuits. An on-chip noise monitor measures in-circuit power supply voltage, while a near-field magnetic probing derives on-board power supply current. The proposed co-simulation well matches the power noise measurements. The proposed AC noise co-simulation will be essentially applicable in the design of PDNs toward on-chip power supply integrity (PSI) and off-chip electromagnetic compatibility (EMC). | ||||||||||
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