Paper 2005/280
Partitioned Cache Architecture as a Side-Channel Defence Mechanism
D. Page
Abstract
Recent research has produced a number of viable side-channel attack methods based on the data-dependant behaviour of microprocessor cache memory. Most proposed defence mechanisms are software based and mainly act to increase the attackers workload rather than obviate the attack entirely. In this paper we investigate the use of a configurable cache architecture to provide hardware assisted defence. By exposing the cache to the processor and allowing it to be dynamically configured to match the needs of a given application, we provide opportunity for higher performance as well as security.
Metadata
- Available format(s)
-
PDF PS
- Category
- Implementation
- Publication info
- Published elsewhere. Unknown where it was published
- Keywords
- side-channel attackcache architecture
- Contact author(s)
- page @ cs bris ac uk
- History
- 2005-08-25: received
- Short URL
- https://ia.cr/2005/280
- License
-
CC BY
BibTeX
@misc{cryptoeprint:2005/280,
author = {D. Page},
title = {Partitioned Cache Architecture as a Side-Channel Defence Mechanism},
howpublished = {Cryptology {ePrint} Archive, Paper 2005/280},
year = {2005},
url = {https://eprint.iacr.org/2005/280}
}